1. Field of the Invention
The present invention relates in general to a sub row decoder circuit for a semiconductor memory device comprising a pull-up transistor for transferring a word line boosting signal to a word line, and a pull-down transistor for transferring a ground voltage to the word line, and more particularly to a sub row decoder circuit in which a source of the pull-down transistor is connected not to the ground voltage but to a pull-up signal, thereby making layout and processing ready, and the pull-up signal and a pull-down signal have the same voltage level in a standby mode, thereby preventing a standby current from being increased although metal lines are short-circuited.
2. Description of the Prior Art
Generally, a row decoder is used in a semiconductor memory device to control word lines. Because of a small space resulting from a high integration of the memory device, it is difficult to lay out one decoder to one word line. For this reason, in most semiconductor memory devices, there has recently been used a hierarchical word line structure where a plurality of hierarchical word line drive circuits share one output of the row decoder and are distinguished from one another by sub row decoders (pxi generators).
The hierarchical word line structure is generally used to loosen a strict metal design rule in the metal strapping of a word line. The metal strapping is to arrange a metal line on a cell array according to a word line pitch and connect it to a word line of polysilicon to reduce a resistance of the word line, thereby increasing a drive speed. Here, the "pitch" signifies the sum of width and space between regularly arranged lines. Because a word line pitch is reduced according to an increase in the integration degree of a semiconductor memory device, the metal strapping increases the possibility of a failure in metal processing, resulting in a reduction in yield. For this reason, the hierarchical word line structure has essentially been applied to semiconductor memory devices, beginning with a 64 Mb dynamic random access memory (DRAM).
The present invention is applicable to all memory devices employing sub row decoder circuits which drive low-order word lines in the hierarchical word line structure.
A conventional low-order word line drive circuit employed in the hierarchical word line structure is generally composed of three NMOS transistors. The low-order word line drive circuit is adapted to perform a double bootstrapping operation to drive a low-order word line at a boosted high voltage level Vpp.
FIG. 1 is a detailed circuit diagram of a conventional sub row decoder circuit for driving a word line WLi. As shown in this drawing, the sub row decoder circuit comprises a first NMOS transistor MN1 connected between an input signal line N1 (first node) and a second node N2, a second NMOS transistor MN2 connected between a word line boosting signal (px+0) line and a word line SWL0, and a third NMOS transistor MN3 connected between the word line SWL0 and a ground voltage Vss. The first NMOS transistor MN1 has its gate for inputting a voltage signal Vx, and the second NMOS transistor MN2 has its gate connected to the second node N2. The third NMOS transistor MN3 has its gate for inputting an inverted one of an input signal on the input signal line N1.
The second NMOS transistor MN2 acts as a pull-up transistor for pulling up the word line SWL0 to a high voltage level Vpp, and the third NMOS transistor MN3 acts as a pull-down transistor for pulling down the word line SWL0 to the ground voltage level Vss (0 V). The first NMOS transistor MN1 acts as a bootstrap transistor for precharging the second node N2. The first NMOS transistor MN1 also acts as a switch for maintaining a voltage at the second node N2 as it is after being bootstrapped. In most cases, Vx=Vcc (logic high) and the second node N2 is precharged with a voltage of Vx-Vt (Vt is a threshold voltage). After the lapse of a predetermined time period from the precharging of the second node N2, the word line boosting signal px+0 is made active to the high voltage level Vpp, thereby causing the second node N2 to be bootstrapped to a voltage of Vpp+Vt or more. As a result, the high voltage Vpp of the word line boosting signal px+0 is directly transferred to the word line SWL0 through the pull-up transistor MN1.
However, the above-mentioned conventional sub row decoder circuit has a disadvantage in that a source of the pull-down transistor is connected to the ground voltage Vss, resulting in a separate ground voltage power line being required.
On the other hand, in a DRAM, polysilicon is generally used as a gate of a cell transistor. However, because the polysilicon is large in resistance, the signal transfer from a row decoder to cells being far away therefrom becomes slow. A metal strapping technique has been proposed to overcome such a problem. However, the metal strapping technique has a difficulty in processing because of a narrower space between metal lines resulting from a higher integration degree. On the other hand, a sub row decoder technique has been proposed to reduce the number of metal lines to half or less to make the processing ready. The sub row decoder technique can conventionally be classified into a CMOS method and an NMOS method. In the CMOS method, the number of metal lines is reduced to 1/4 to make the metal processing ready. Further, since the metal lines have the same voltage level in a standby mode, a standby current is not increased although the metal lines are short-circuited. However, a separate N-well is required because of the use of PMOS, resulting in an increase in occupied area. In the NMOS method, no separate well is required, resulting in a reduction in occupied area. However, since the metal lines have different voltage levels in the standby mode, the standby current is increased if the metal lines are short-circuited. The increase of the standby current makes the memory device useless even if it is repaired.